This invention is in the field of semiconductor integrated circuits, and is more specifically directed to integrated circuits having electrostatic discharge (ESD) protection circuitry and techniques for protecting integrated circuits from damage caused by electrostatic discharge events.
Modern high-density integrated circuits (ICs) are known to be vulnerable to damage from the electrostatic discharge (ESD) of a charged body. ESD damage occurs when the amount of charge exceeds the capability of the conduction path through the integrated circuit. In the MOS transistor context, the typical ESD failure mechanisms include thermal runaway resulting in junction shorting, and dielectric breakdown resulting in gate-junction shorting.
To avoid damage from ESD, modern integrated circuits may incorporate ESD protection devices at each external terminal (viz., pin pad). ESD protection devices generally operate by providing a high current capacity conduction path, so that a brief but massive ESD event may be safely conducted away from vulnerable. In some cases, ESD protection is inherent to the particular terminal, as in the case of a power supply terminal which may provide an extremely large p-n junction capable of conducting the ESD charge. Input/output (I/O) terminals, on the other hand, typically have separate ESD protection devices added in parallel to the functional terminals. The ideal ESD protection device turns on quickly in response to an ESD event, with large conduction capability, but remains off and presents no significant load during normal operation.
The high operating voltage and failsafe design constraints have generally been addressed through the use of drain-extended MOS transistors (referred to as DeMOS transistors, or DeNMOS transistors in the case of n-channel DeMOS devices). A conventional drain-extended transistor has its drain region located within a well of the same conductivity type; for example, in the n-channel case, the n-type drain region is placed within a relatively lightly-doped n-type well. The increased drain-to-substrate junction area provided by the well, along with the reduced dopant concentration at the drain-to-substrate junction, greatly increases the junction breakdown voltage, permitting high voltage operation of the transistor while tolerating voltage excursions at the drain that can occur in the absence of a clamp. DeMOS transistors also enable the use of thinner gate dielectric (e.g. oxide) because the voltage drop across the depletion region of the well reduces the electric field at the drain-side edge of the gate dielectric, and thus reduces the number of channel “hot” carriers that are produced. This reduction in “hot” carrier effects, specifically threshold voltage shift, enables the construction of reliable transistors with extremely thin gate dielectrics. DeMOS devices also present high output impedance, which is especially attractive in using the device in analog circuits. DeMOS transistors are therefore very attractive for use at input/output (I/O) terminals of modern integrated circuits.
It has been observed, however, that DeMOS devices themselves provide relatively poor inherent ESD protection. One mode of operation for ESD protection structures comprises the elevation of the substrate potential (e.g. to achieve VSUB>1V) during ESD conditions. This substrate bias improves the response of the ESD protection device, while not generally affecting normal operation of the integrated circuit being protected.
In one known substrate elevation embodiment, the ESD cell comprises an NMOS transistor and an RC-triggered pump transistor which is operable to raise the substrate potential of the NMOS transistor during ESD events by forcing current directly into the floating substrate. In another substrate elevation arrangement, the ESD cell comprises an NMOS transistor and an Nwell diode connected to the supply line. When an ESD event strikes this cell, the charging of the supply capacitance forces substrate current from the parasitic pnp embedded in the Nwell diode into the NMOS substrate, thus raising the substrate potential.
However, known ESD protection structures are subject to deficiencies, such as: relatively large circuit area required; full protection for only a portion (e.g. beginning) of the ESD pulse; lack applicability to failsafe applications (e.g. a direct DC path to the power supply is not available); significant capacitive loading; and need for extra biasing circuit or connections.
What is needed is a new ESD protection structure and method of protecting functional circuitry against ESD induced damage that eliminates or reduces the deficiencies listed above.